The present invention relates to an oscillator control apparatus.
An All Digital Phase Locked Loop (ADPLL) circuit, in which all of control signals in a phase locked loop (PLL) are digitized, has been recently used in a radio communication apparatus such as radio LAN equipment (see, for example, Japanese Patent Application Laid-open No. 2009-21954). In the ADPLL circuit, an analog circuit is replaced with a digital circuit, and therefore, the advance of processes can save a space and electric power.
The ADPLL circuit includes a digital loop filter, a digitally-controlled oscillator (DCO), a counter, and a time-to-digital converter (TDC). The counter is adapted to count outputs from the DCO and to output a count in response to a reference signal synchronized with the output from the DCO. The TDC takes a phase difference of 1 cycle or less of the output from the DCO in synchronism with the reference signal. A comparison result (i.e., a difference) between a value obtained by adding the count and the phase difference and a phase control signal is applied to the digital loop filter. An oscillation frequency of the DCO is controlled based on the output from the digital loop filter.
The output from the DCO is asynchronous to the reference signal. In other words, in the ADPLL circuit, outputs from the two circuits (i.e., the counter and the TDC) operative by an asynchronous clock are added. As a consequence, a value read by the counter is shifted, thereby raising a possibility of instable operation of the PLL.